In 4-pin slave mode, UCxSTE is used by the slave to enable the transmit and receive operations and is provided by the SPI master. When UCxSTE is in the slave-active state, the slave operates normally. When UCxSTE is in the slave-inactive state:
- Any receive operation in progress on UCxSIMO is halted.
- UCxSOMI is set to the input direction.
- The shift operation is halted until the UCxSTE line transitions into the slave transmit active state. The UCxSTE input signal is not used in 3-pin slave mode.
When the USCI module is enabled by clearing the UCSWRST bit, it is ready to receive and transmit. In master mode, the bit clock generator is ready but is not clocked nor producing any clocks. In slave mode, the bit clock generator is disabled and the clock is provided by the master. A transmit or receive operation is indicated by UCBUSY = 1. A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated.
In master mode, writing to UCxTXBUF activates the bit clock generator, and the data begins to transmit. In slave mode, transmission begins when a master provides a clock and, in 4- pin mode, when the UCxSTE is in the slave-active state.
The SPI receives data when a transmission is active. Receive and transmit operations operate concurrently.