To get the full accuracy for the ADC measurements, some timing restrictions need
to be considered: If the ADCLK frequency is chosen too high, an accurate 14- or 12-bit conversion cannot be assured. This is due to the internal time constants of the sampling analog input and conversion network. The ADC is still functional, but the conversion results show a higher noise level (larger bandwidth of results for the same input signal) with higher conversion frequencies. If the ADCLK frequency is chosen too low, then an accurate 14- or 12-bit conversion cannot be assured due to charge losses within the capacitor array of the ADC. This remains true even if the input signal is constant during the sampling time.
After the ADC module has been activated by resetting the power-down bit, at least 6 s (power-up time in Figure 9) must elapse before a conversion is started. This is necessary to allow the internal biases to settle. This power-up time is automatically ensured for MCLK frequencies up to 2.5 MHz if the measurement is started the usual way: by separation of the definition and the start of the measurement inside of the subroutine:
MOV #xxx,&ACTL ; Define ADC measurement
CALL #MEASR; Start measurement with SOC=1, ADC result in ADAT
If higher MCLK frequencies are used, then a delay needs to be inserted between the definition and the start of the measurement. See the source of the MEASR subroutine in the section
The number n of additional delay cycles (MCLK cycles) needed is n MCLK) –15
If the input voltage changes very fast, then the range sample and the conversion sample may be captured in different ranges. See section 2.2.1 if this cannot be tolerated. For applications like an electricity meter, this doesn’t matter: the error occurs as often for the increasing voltage as for the decreasing voltage so the resulting error is zero.
After the start of conversion, no modification of the ACTL register is allowed until the conversion is complete. Otherwise, the ADC result will be invalid. The previously described timing errors lead to spikes in the ADC characteristic: the ADC seems to get caught at certain steps of the ADC. This is not an ADC error; the reasons are violations of the ADC timing restrictions. See Figure 4. The x-axis shows the range A from step 0 to step 4096, the y-axis shows the ADC error (steps).
The ADC always runs at a clock rate set to one-twelfth of the selected ADCLK.
The frequency of the ADCLK should be chosen to meet the conversion time defined in the electrical characteristics (see datasheet). The correct frequency for the ADCLK can be selected by two bits (ADCLK) in the control register ACTL. The MCLK clock signal is then divided by a factor of 1, 2, 3, or 4. See Section 3.5.
