• Microinstructions are stored in control memory in groups, with each group specifying a routine.
  • Each computer instruction has its own microprogram routine in control memory to generate the microoperations that execute the instruction.
  • To appreciate the address sequencing in a microprogram control unit:
    • An initial address is loaded into the control address register when power is turned on in the computer.
    • This address is usually the address of the first microinstruction that activates the instruction fetch routine.
    • The control memory next must go through the routine that determines the effective address of the operand.
    • The next step is to generate the microoperations that execute the instruction fetched from memory.
  • The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process.
  • The address sequencing capabilities required in a control memory are:
    • Incrementing of the control address register 
    • Unconditional branch or conditional branch, depending on status bit conditions
    • A mapping process from the bits of the instruction to an address for control memory
    • A facility for subroutine call and return
  • 3-2 shows a block diagram of a control memory and the associated hardware needed for selecting the next microinstruction address.
  • The microinstruction in control memory contains
    • a set of bits to initiate microoperations in computer registers
    • Other bits to specify the method by which the next address is obtained

Sequencing Capabilities Required in Control Storage

  • Incrementing of the control address register
  • Unconditional and conditional branches
  • A mapping process from the bits of the machine instruction to an address for control memory
  • A facility for subroutine call and return

                             Fig 3-2: Selection of address for control memory

Conditional Branching

  • The branch logic of 3-2 provides decision-making capabilities in the control unit.
  • The status conditions are special bits in the system that provides parameter information.
    • eg. the carry-out, the sign bit, the mode bits, and input or output status
  • The status bits, together with the field in the microinstruction that specifies a branch address, control the conditional branch decisions generated in the branch logic.
  • The branch logic hardware may be implemented by multiplexer.
    • Branch to the indicated address if the condition is met;
    • Otherwise, the address register is incremented.
  • An unconditional branch microinstruction can be implemented by loading the branch address from control memory into the control address register.
  • If Condition is true, then Branch (address from the next address field of the current microinstruction)

         else Fall Through

  • Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc.

Unconditional Branch

  • Fixing the value of one status bit at the input of the multiplexer to 1

Mapping of Instructions

  • A special type of branch exists when a microinstruction specifies a branch to the first word in control memory where a microprogram routine for an instruction is located.
  • The status bits for this type of branch are the bits in the operation code part of the instruction.
  • One simple mapping process that converts the 4-bit operation code to a 7-bit address for control memory is shown in Fig. 3-3.
    • Placing a 0 in the most significant bit of the address
    • Transferring the four operation code bits
    • Clearing the two least significant bits of the control address register
  • This provides for each computer instruction a microprogram routine with a capacity of four microinstructions.
    • If the routine needs more than four microinstructions, it can use addresses 1000000 through 1111111.
    • If it uses fewer than four microinstructions, the unused memory locations would be available for other routines.
  • One can extend this concept to a more general mapping rule by using a ROM or programmable logic device (PLD) to specify the mapping function.

                     Fig 3-3: Mapping from instruction code to microinstruction address

                                                       Fig 3-3 (a): Direct mapping

       Fig 3-3 (b): Mapping Function Implemented by ROM and PLD

Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram.

Subroutine

  • Subroutines are programs that are used by other routines to accomplish a particular task.
  • Microinstructions can be saved by employing subroutines that use common sections of microcode.
  • eg. effective address computation
  • The subroutine register can then become the source for transferring the address for the return to the main routine.
  • The best way to structure a register file that stores addresses for subroutines is to organize the registers in a last-in, first-out (LIFO) stack.