The MSP430 concept differs considerably from other microcontrollers and offers some significant advantages over more traditional designs.

RISC Architecture Without RISC Disadvantages

Typical RISC architectures show their highest performance in calculation-intensive applications in which several registers are loaded with input data, all calculations are made within the registers, and the results are stored back in RAM. Memory accesses (using addressing modes) are necessary only for the LOAD instructions at the beginning and the STORE instructions at the end of the calculations. The MSP430 can be programmed for such an operation, for example, performing a pure calculation task in the floating point without any I/O accesses.

Pure RISC architectures have some disadvantages when running real-time applications that require frequent I/O accesses, however. Time is lost whenever an operand is fetched and loaded from RAM, modified, and then stored back into RAM.

The MSP430 architecture was designed to include the best of both worlds, taking advantage of RISC features for fast and efficient calculations, and addressing modes for real-time requirements:

  1. The RISC architecture provides a limited number of powerful instructions, numerous registers, and single-cycle execution times.
  2. The more traditional microcomputer features provide addressing modes for all instructions. This functionality is further enhanced with 100% orthogonality, allowing any instruction to be used with any addressing mode.

Real-Time Capability With Ultra-Low Power Consumption

The design of the MSP430 was driven by the need to provide full real-time capability while still exhibiting extremely low power consumption. Average power consumption is reduced to the minimum by running the CPU and certain other functions of the MSP430 only when it is necessary. The rest of the time (the majority of the time), power is conserved by keeping only selected low-power peripheral functions active. But to have a true real-time capability, the device must be able to shift from a low-power mode with the CPU off to a fully active mode with the CPU and all other device functions operating nominally in a very short time. This was accomplished primarily with the design of the system clock:

  1. No secohigh-frequency crystal is used — inherent delays can range from 20 ms to 200 ms until oscillator stability is reached
  2. Instead, a sophisticated FLL system clock generator is used — generator output frequency (MCLK) reaches the nominal frequency within 8 cycles after activation from low power mode 3 (LPM3) or sleep mode
  3.   This design provides real-time capability almost immediately after the device comes out of an LPM — as if the CPU is always active. Only two additional MCLK cycles (2   s @ fC = 1 MHz) are necessary to get the device from LPM3 to the first instruction of the interrupt handler.

Digitally Controlled Oscillator Stability:

The digitally controlled oscillator (DCO) is voltage and temperature-dependent, which does not mean that its frequency is not stable. During the active mode, the integral error is corrected to approximately zero every 30.5 s. This is accomplished by switching between two different DCO frequencies. One frequency is higher than the programmed MCLK frequency and the other is lower, causing the errors to essentially cancel out. The two DCO frequencies are interlaced as much as possible to provide the smallest possible error at any given time. See System Clock Generator for more information.

Stack Processing Capability:

The MSP430 is a true stack processor, with most of the seven addressing modes implemented for the stack pointer (SP) as well as the other CPU registers (PC and R4 through R15). The capabilities of the stack include:

  1. Free access to all items on the stack — not only to the top of the stack (TOS)
  2. Ability to modify subroutine and interrupt return addresses located on the stack
  3. Ability to modify the stored status register of interrupt returns located on the stack
  4. No special stack instructions — all of the implemented instructions may be used for the stack and the stack pointer
  5. Byte and word capability for the stathe ck
  6. Free mix of subroutine and interrupt handling — as long as no stack modification (PUSH, POP, etc.) is made, no errors can occur