Memory Organization
- Logical separation of program and data memory
- Separate address spaces for Program (ROM) and Data (RAM) Memory
Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU
Program Memory
- Only be read, not written to
- The address space is 16-bit, so maximum of 64K bytes
- Up to 4K bytes can be on-chip (internal) of 8051 core
- PSEN (Program Store Enable) is used for access to external Program Memory
Data Memory
- Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions
- There is also a number of Special Function Registers (SFRs)
- Internal Data Memory contains four banks of eight registers and a special 32- byte long segment which is bit addressable by 8051 bit-instructions
- External memory of maximum 64K bytes is accessible by “movx”
Interrupt Structure
- The 8051 provides 4 interrupt sources
- Two external interrupts
- Two timer interrupts
Port Structure
- The 8051 contains four I/O ports
- All four ports are bidirectional
- Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer
- Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory
- Accessing external memory works like this
- Port 0 outputs the low byte of external memory address (which is timemultiplexed with the byte being written or read)
- Port 2 outputs the high byte (only needed when the address is 16 bits wide)
- Port 3 pins are multifunctional
- The alternate functions are activated with the 1 written in the corresponding bit in the port SFR
Timer/Counter
- The 8051 has two 16-bit Timer/Counter registers
- Timer 0
- Timer 1
- Both can work either as timers or event counters
- Both have four different operating modes