 Pipeline arithmetic units are usually found in very high speed computers
 Floating–point operations, multiplication of fixedpoint numbers, and similar computations in scientific problem
 Floating–point operations are easily decomposed into sub operations.
 An example of a pipeline unit for floatingpoint addition and subtraction is showed in the following:
 The inputs to the floatingpoint adder pipeline are two normalized floatingpoint binary number
X = A´ 2^{a}
Y = B ´ 2^{b}
 A and B are two fractions that represent the mantissas

 The floatingpoint addition and subtraction can be performed in four segments, as shown in Fig. 46.
 The suboperations that are performed in the four segments are:
 Compare the exponents
 The larger exponent is chosen as the exponent of the result.
 Align the mantissas
 The exponent difference determines how many times the mantissa associated with the smaller exponent must be shifted to the right.
 Add or subtract the mantissas and b are the exponents
 Normalize the result
 Compare the exponents
 When an overflow occurs, the mantissa of the sum or difference is shifted right and the exponent incremented by one.
 If an underflow occurs, the number of leading zeros in the mantissa determines the number of left shifts in the mantissa and the number that must be subtracted from the exponent.
 The following numerical example may clarify the suboperations performed in each segment.
 The comparator, shift, adder, subtractor, incrementer, and decrementer in the floatingpoint pipeline are implemented with combinational circuits.
 Suppose that the time delays of the four segments are t_{1}=60ns, t_{2}=70ns, t_{3}=100ns, t_{4}=80ns, and the interface registers have a delay of t_{r}=10ns

 Pipeline floatingpoint arithmetic delay: t_{p}=t_{3}+t_{r}=110ns
 Nonpipeline floatingpoint arithmetic delay: t_{n}=t_{1}+t_{2}+t_{3}+t_{4}+t_{r}=320ns
 Speedup: 320/110=2.9
Fig 46: Pipeline for floating point addition and subtraction