• A bus is a communication pathway connecting two or more devices
  • Usually broadcast (all components see signal)
  • Often grouped
    • A number of channels in one bus
    • eg. 32 bit data bus is 32 separate single bit channels
  • Power lines may not be shown
  • There are a number of possible interconnection systems
  • Single and multiple BUS structures are most common
  • eg. Control/Address/Data bus (PC)
  • eg. Unibus (DEC-PDP)
  • Lots of devices on one bus leads to:
    • Propagation delays
    • Long data paths mean that co-ordination of bus use can adversely affect performance
    • If aggregate data transfer approaches bus capacity
  • Most systems use multiple buses to overcome these problems

Fig: Bus Interconnection Scheme

  • Data Bus
    • Carries data
      • Remember that there is no difference between “data” and “instruction” at this level
    • Width is a key determinant of performance
      • 8, 16, 32, 64 bit
    • Address Bus
      • Identify the source or destination of data
      • g. CPU needs to read an instruction (data) from a given location in memory
      • Bus width determines maximum memory capacity of system
        • g. 8080 has 16 bit address bus giving 64k address space
      • Control Bus
        • Control and timing information
          • Memory read
          • Memory write
          • I/O read
          • I/O write
          • Transfer ACK
          • Bus request
          • Bus grant
          • Interrupt request
          • Interrupt ACK
          • Clock
          • Reset

Multiple Bus Hierarchies

  • A great number of devices on a bus will cause performance to suffer
    • Propagation delay - the time it takes for devices to coordinate the use of the bus
    • The bus may become a bottleneck as the aggregate data transfer demand approaches the capacity of the bus (in available transfer cycles/second)
  • Traditional Hierarchical Bus Architecture
    • Use of a cache structure insulates CPU from frequent accesses to main memory
    • Main memory can be moved off local bus to a system bus
    • Expansion bus interface
      • buffers data transfers between system bus and I/O controllers on expansion bus
    • insulates memory-to-processor traffic from I/O traffic

Traditional Hierarchical Bus Architecture Example

  • High-performance Hierarchical Bus Architecture
    • Traditional hierarchical bus breaks down as higher and higher performance is seen in the I/O devices
    • Incorporates a high-speed bus
      • specifically designed to support high-capacity I/O devices
    • brings high-demand devices into closer integration with the processor and at the same time is independent of the processor
    • Changes in processor architecture do not affect the high-speed bus, and vice versa
      • Sometimes known as a mezzanine architecture

High-performance Hierarchical Bus Architecture Example

Elements of Bus Design

  • Bus Types
    • Dedicated
      • Separate data & address lines
    • Multiplexed
      • Shared lines
      • Address valid or data valid control line
      • Advantage - fewer lines
      • Disadvantages
        • More complex control
        • Ultimate performance
      • Bus Arbitration
        • More than one module controlling the bus
          • eg. CPU and DMA controller
        • Only one module may control bus at one time
        • Arbitration may be centralised or distributed
      • Centralised Arbitration
        • Single hardware device controlling bus access
          • Bus Controller
          • Arbiter
        • May be part of CPU or separate
      • Distributed Arbitration
  • Each module may claim the bus
  • Control logic on all modules
  • Timing
    • Co-ordination of events on bus
    • Synchronous
      • Events determined by clock signals
      • Control Bus includes clock line
      • A single 1-0 is a bus cycle
      • All devices can read clock line
      • Usually sync on leading edge
      • Usually a single cycle for an event
    • Bus Width
      • Address: Width of address bus has an impact on system capacity e. wider bus means greater the range of locations that can be transferred.
      • Data: width of data bus has an impact on system performance e. wider bus means number of bits transferred at one time.
    • Data Transfer Type
      • Read
      • Write
      • Read-modify-write
      • Read-after-write
      • Block