Up to seven identical capture/compare blocks, TAxCCRn (where n = 0 to 7), are present in Timer_A. Any of the blocks may be used to capture the timer data or to generate time intervals.

Capture Mode

The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCIS bits. The CM bits select the capture edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture occurs:

  • The timer value is copied into the TAxCCRn register.
  • The interrupt flag CCIFG is set.

The input signal level can be read at any time via the CCI bit. Devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals.

The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit synchronizes the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended (see Figure 17-10).

Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs.COV must be reset with software.

Capture Initiated by Software

 Captures can be initiated by software. The CMx bits can be set for capture on both edges. SoftThe softwaren sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state:

MOV #CAP+SCS+CCIS1+CM_3,&TA0CCTL1 ; Setup TA0CCTL1, synch. capture mode;

Event trigger on both edges of capture input. XOR #CCIS0,&TA0CCTL1 ; TA0CCR1 = TA0R

Capture Initiated by Software

In general, changing capture inputs while in capture mode may cause unintended capture events. For this scenario, switching the capture input between VCC and GND, disaand bling the capture mode is not required.

Compare Mode

The compare mode is selected when CAP = 0. The compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TAxR counts to the value in a TAxCCRn, where n represents the specific capture/compare register.

  • Interrupt flag CCIFG is set.
  • Internal signal EQUn = 1.
  • EQUn affects the output according to the output mode.
  • The input signal CCI is latched into SCCI.

Output Unit

Each capture/compare block contains an output unit. The output unit is used to generate output signals, such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUn signals.

Output Modes

The output modes are defined by the OUTMOUT MODs and are described in Table 17-2. The OUTnoutnal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0 because EQU ofn = EQU0.

Output Example: Timer in Up Mode

The OUTnoutnal is changed when the timer counts up to the TAxCCRn value and rolls from TAxCCR0 to zero, depending on the output mode. An example is shown in FiguFigures12 using TAxCCR0 and TAxCCR1.

Output Example : Timer in Continuous Mode

The OUTnoutnal is changed when the timer reaches the TAxCCRn and TAxCCR0 values, depending on the output mode. An example is shown in FiguFigures13 using TAxCCR0 and TAxCCR1.

Output Example : Timer in Up/Down Mode

The OUTn signal outages when the timer equals TAxCCRn in both count direction directions timer equals TAxCCR0, depending on the output mode. An example is shown in Figure 17-14Figures TAxCCR0 and TAxCCR2.