The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the – terminal, the comparator output CBOUT is high. The comparator can be switched on or off using the control bit CBON. The comparator should be switched off when not in use to reduce current consumption. When the comparator is switched off, CBOUT is always low. The bias current of the comparator is programmable.
Analog Input Switches
The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the CBIPSELx and CBIMSELx bits. The comparator terminal inputs can be controlled individually. The CBIPSELx/CBIMSELx bits allow:
- Application of an external signal to the + and – terminals of the comparator
- Application of an external current source (for example, a resistor) to the + or – terminal of the comparator
- The mapping of both terminals of the internal multiplexer to the outside
Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path The CBEX bit controls the input multiplexer, permuting the input signals of the comparator's + and – terminals. Additionally, when the comparator terminals are permuted, the output signal from the comparator is inverted too. This allows the user to determine or compensate for the comparator input offset voltage.
The Px.y pins associated with a comparator channel are enabled by the CBIPSELx or CBIMSELx bits to disable its digital components while used as comparator input. Only one of the comparator input pins is selected as input to the comparator by the input multiplexer at a time.
Input Short Switch
The CB SHORT bit shorts the Comp_B inputs. This can be used to build a simple sample-and-hold for the Comparator
input switches in series with the short switch (Ri), and the resistance of the external source (RS). The total internal resistance (RI) is typically in the range of 1 kΩ. The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the following equation:
Tau = (RI + RS) × CS
Depending on the required accuracy, 3 to 10 Tau should be used as a sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charged to more than 99%, and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy.
The output of the comparator can be used with or without internal filtering. When the control bit CBF is set, the output is filtered with an on-chip RC filter. The delay of the filter can be adjusted in four different steps. All comparator outputs are oscillating if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross-coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figures 32-3. The comparator output oscillation reduces the accuracy and resolution of the comparison result. Selecting the output filter can reduce errors associated with comparator oscillation.
Reference Voltage Generator
The Comp_B reference block diagram is shown
The voltage reference generator is used to generate VREF, which can be applied to either comparator input terminal. The CBREF1x (VREF1) and CBREF0x (VREF0) bits control the output of the voltage generator. The CBRSEL bit selects the comparator terminal to which VREF is applied. If external signals are applied to both comparator input terminals, the internal reference generator should be turned off to reduce current consumption. The voltage reference generator can generate a fraction of the device's VCC or of the voltage reference of the integrated precision voltage reference source. Vref1 is used while CBOUT is 1 and Vref0 is used while CBOUT is 0. This allows the generation of a hysteresis without using external components.
Comp_B, Port Disable Register CBCTL3
The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic currents can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption.
The CBPDx bits in the CBCTL3 register, when set, disable the corresponding Px.y input buffer as shown in Figure 32-5. When current consumption is critical, any Px.y pin connected to analog signals should be disabled with their associated CBPDx bits. Selecting an input pin to the comparator multiplexer with the CBIPSEL or CBIMSEL bits automatically disables the input buffer for that pin, regardless of the state of the associated CBPDx bit.
One interrupt flag and one interrupt vector are associated with Comp_B. The interrupt flag CBIFG is set on either the rising or falling edge of the comparator output, selected by the CBIES bit. If both the CBIE and the GIE bits are set, then the CBIFG interrupt flag generates an interrupt request.
NOTE: Changing the value of the CBIES bit might set the comparator interrupt flag CBIFG. This can happen even when the comparator is disabled (CBON = 0). It is recommended to clear CBIFG after configuring the comparator for proper interrupt behavior during operation.
Comp_B Used to Measure Resistive Elements
The Comp_B can be optimized to precisely measure resistive elements using single slope analog-to digital conversion. For example, the temperature can be converted into digital data using a thermistor, by comparing the thermistor's capacitor discharge time to that of a reference resistor as shown in Figure 32-A reference resistor Reef is compared to Rmeas.
The resources used to calculate the temperature sensed by Rmeas are:
- Two digital I/O pins charge and discharge the capacitor.
- I/O is set to output high (VCC) to charge the capacitor and reset to discharge.
- I/O is switched to high-impedance input with CBPDx set when not in use.
- One output charges and discharges the capacitor through Reef.
- One output discharges capacitor through Rmeas.
- The + terminal is connected to the positive terminal of the capacitor.
- The – terminal is connected to a reference level, for example, 0.25 × VCC.
- The output filter should be used to minimize switching noise.
- CBOUT is used to gate Timer_A CCI1B, capturing capacitor discharge time.
More than one resistive element can be measured. Additional elements are connected to CB0 with available I/O pins and switched to high impedance when not being measured. The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figures 32-7.
The VCC voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio