• The Control Unit (CU) and the Arithmetic and Logic Unit (ALU) constitute the Central Processing Unit (CPU)
  • Data and instructions need to get into the system and results need to get out
    • Input/output (I/O module)
  • Temporary storage of code and results is needed
    • Main memory (RAM)
  • Program Concept
    • Hardwired systems are inflexible
    • General purpose hardware can do different tasks, given correct control signals
    • Instead of re-wiring, supply a new set of control signals

Fig: Hardware and Software Approaches

 

Computer Function

The basic function performed by a computer is execution of a program, which consists of a set of instructions stored in memory.

  • Two steps of Instructions Cycle:
    • Fetch
    • Execute

                                             Fig: Basic Instruction Cycle

  • Fetch Cycle
    • Program Counter (PC) holds address of next instruction to fetch
    • Processor fetches instruction from memory location pointed to by PC
    • Increment PC
      • Unless told otherwise
    • Instruction loaded into Instruction Register (IR)
  • Execute Cycle
    • Processor interprets instruction and performs required actions, such as:
      • Processor - memory
        • data transfer between CPU and main memory
      • Processor - I/O
        • Data transfer between CPU and I/O module
      • Data processing
        • Some arithmetic or logical operation on data
      • Control
        • Alteration of sequence of operations
        • g. jump
      • Combination of above Example of program execution.

Example of program execution.

Fig: Example of program execution (consists of memory and registers in hexadecimal)

  • The PC contains 300, the address of the first instruction. The instruction (the value 1940 in hex) is loaded into IR and PC is incremented. This process involves the use of MAR and MBR.
  • The first hexadecimal digit in IR indicates that the AC is to be loaded. The remaining three hexadecimal digits specify the address (940) from which data are to be loaded.
  • The next instruction (5941) is fetched from location 301 and PC is incremented.
  • The old contents of AC and the contents of location 941 are added and the result is stored in the AC.
  • The next instruction (2941) is fetched from location 302 and the PC is incremented.
  • The contents of the AC are stored in location 941.

                          Fig: Instruction cycle state diagram Interrupts:

  • Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing
  • Program
    • eg. overflow, division by zero
  • Timer
    • Generated by internal processor timer
    • Used in pre-emptive multi-tasking
  • I/O
    • from I/O controller
  • Hardware failure
    • eg. memory parity error

                         Figure: Program flow of control without and with interrupts

  • Instruction Cycle
    • Added to instruction cycle
    • Processor checks for interrupt
      • Indicated by an interrupt signal
    • If no interrupt, fetch next instruction
    • If interrupt pending:
      • Suspend execution of current program
      • Save context
      • Set PC to start address of interrupt handler routine
      • Process interrupt
      • Restore context and continue interrupted program

                                 Fig: Transfer of control via interrupts

                                                       Fig: Instruction Cycle with Interrupts

 

                                   Fig: Instruction cycle state diagram, with interrupts

  • Multiple Interrupts
    • Disable interrupts (approach #1)
      • Processor will ignore further interrupts whilst processing one interrupt
      • Interrupts remain pending and are checked after first interrupt has been processed
      • Interrupts handled in sequence as they occur
    • Define priorities (approach #2)
      • Low priority interrupts can be interrupted by higher priority interrupts
      • When higher priority interrupt has been processed, processor returns to previous interrupt