Introduction

The DMA controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC conversion memory to RAM. Devices that contain a DMA controller may have up to eight DMA channels available. Therefore, depending on the number of DMA channels available, some features described in this chapter are not applicable to all devices. See the device-specific data sheet for number of channels supported.

Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode, without having to awaken to move data to or from a peripheral.

DMA controller features include:

  • Up to eight independent transfer channels
  • Configurable DMA channel priorities
  • Requires only two MCLK clock cycles per transfer
  • Byte or word and mixed byte and word transfer capability
  • Block sizes up to 65535 bytes or words
  • Configurable transfer trigger selections
  • Selectable-edge or level-triggered transfer
  • Four addressing modes
  • Single, block, or burst-block transfer modes