• Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc.
  • DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device
  • CPU initializes the DMA controller by sending a memory address and the number of words to be transferred
  • Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks

The transfer of data between the peripheral and memory without the interaction of CPU and letting the peripheral device manage the memory bus directly is termed as Direct Memory Access (DMA).


                                             Fig: CPU bus signal for DMA transfer

The two control signals Bus Request and Bus Grant are used to fascinate the DMA transfer. The bus request input is used by the DMA controller to request the CPU for the control of the buses. When BR signal is high, the CPU terminates the execution of the current instructions and then places the address, data, read and write lines to the high impedance state and sends the bus grant signal. The DMA controller now takes the control of the buses and transfers the data directly between memory and I/O without processor interaction. When the transfer is completed, the bus request signal is made low by DMA. In response to which CPU disables the bus grant and again CPU takes the control of address, data, read and write lines.


The transfer of data between the memory and I/O of course facilitates in two ways which are DMA Burst and Cycle Stealing.

DMA Burst: The block of data consisting a number of memory words is transferred at a time.

Cycle Stealing: DMA transfers one data word at a time after which it must return control of the buses to the CPU.

  • CPU is usually much faster than I/O (DMA), thus CPU uses the most of the memory cycles
  • DMA Controller steals the memory cycles from CPU
  • For those stolen cycles, CPU remains idle
  • For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time

DMA Controller

The DMA controller communicates with the CPU through the data bus and control lines. DMA select signal is used for selecting the controller, the register select is for selecting the register. When the bus grant signal is zero, the CPU communicates through the data bus to read or write into the DMA register. When bus grant is one, the DMA controller takes the control of buses and transfers the data between the memory and I/O.


                                                                  Fig: Block diagram of DMA controller

The address register specifies the desired location of the memory which is incremented after each word is transferred to the memory. The word count register holds the number of words to be transferred which is decremented after each transfer until it is zero. When it is zero, it indicates the end of transfer. After which the bus grant signal from CPU is made low and CPU returns to its normal operation. The control register specifies the mode of transfer which is Read or Write.

DMA Transfer

  • DMA request signal is given from I/O device to DMA controller.
  • DMA sends the bus request signal to CPU in response to which CPU disables its current instructions and initialize the DMA by sending the following information
    • The starting address of the memory block where the data are available (for read) and where data to be stored (for write)
    • The word count which is the number of words in the memory block
    • Control to specify the mode of transfer
    • Sends a bust grant as 1 so that DMA controller can take the control of the buses
    • DMA sends the DMA acknowledge signal in response to which peripheral device puts the words in the data bus (for write) or receives a word from the data bus (for read).


                                                      Fig: DMA transfer in a computer system

DMA Operation

  • CPU tells DMA controller:-
    • Read/Write
    • Device address
    • Starting address of memory block for data
    • Amount of data to be transferred
  • CPU carries on with other work
  • DMA controller deals with transfer
  • DMA controller sends interrupt when finished