The MSP430x4xx family has the more sophisticated FLL+ clock module. Much of this, such as LFXT1 and XT2, is similar to the MSP430F2xx but the registers and bits have different names. For example, the load capacitance for a low-frequency crystal is controlled by the XCAPxPF bits in the FLL_CTL0 register. There are no dividers for the internal clocks but the external signal from ACLK can be divided.

The main difference is of course the *frequency-locked loop*. This is hardware that aims to lock the frequency of the DCO to that of LFXT1. The DCO in the FLL+ has only five ranges but each covers a factor of about 10 in frequency and is divided into 29 taps. The modulator works in the same way as that in the BCM+. The name makes the FLL sound complicated but its basic mode of operation is simple. It relies on a feedback loop shown in Figure 5.11:

- The range of the DCO is set with the FN_x bits and modulation may be suppressed by setting SCFQ_M. Its output is at a frequency
*f*DCO.

- This is divided by a factor
*D*specified with the FLLDx bits. This gives a frequency of*f*DCO*/D*. - The divided signal is fed into a counter with a period of
*(N*+1*)*, where*N*is stored in the lower 7 bits of SCFQCTL. - The counter overflows at a frequency of
*f*DCO*/*[*D(N*+1*)*], which is compared with the frequency of ACLK.

The controller adjusts *f*DCO one step up or down with the aim of bringing these frequencies together. Thus the frequency of the DCO itself is given by *f*DCO = *D(N *+1*)f*ACLK when the loop has locked but this is not necessarily the frequency of the output. DCOCLK can be taken either before or after the divider according to the setting of the DCOPLUS bit. When this bit is clear, the divided output is taken and

The nomenclature is a little confusing because the divider apparently increases the frequency of the clock, which is the opposite of the usual case. Do not forget the *(N *+1*) *in the multiplier—it is not just *N*. There are 7 bits for *N *in SCFQCTL so the maximum value of *(N *+1*) *is 128 and the maximum value of *f*DCOCLK is 4MHz (binary megahertz to be precise) if *f*ACLK = 32KHz and DCOPLUS = 0. This is well below the maximum frequency at which the CPU can run, which is 16MHz in newer devices. DCOPLUS must be set for higher frequencies. Itshows an example where DCOPLUS is used to raise the frequency of DCOCLK.

After a PUC, the FLL+ is configured for its lowest range of 0.65–6.1 MHz, DCOPLUS is clear, *D *= 2, and *N *= 31. This gives *f*DCOCLK = 32*f*ACLK, which is a binary megahertz

(220 Hz) if *f*ACLK = 32 KHz. The DCO itself runs at twice the frequency of DCOCLK because of *D*.

It takes some time for the FLL to lock and a software delay loop can be used to wait for this (and for the crystal to stabilize). The FLL starts at the bottom of its range after a PUC.

It may have to reach the top of the range for the desired frequency, which requires up to 32×28 ≈ 900 steps. This is the number of modulator steps times the number of usable taps—the highest tap is not useful because it cannot be modulated. Each step takes one cycle of ACLK, which corresponds to *(N *+1*) *or *D(N *+1*) *cycles of MCLK. This tells us the length of the delay loop needed. A simple loop takes three cycles of MCLK per iteration, as we found in Listing 4.12, so the stabilization loop needs about 300*(N *+1*) *or 300*D(N *+1*) *iterations. This is about 10,000≈

0x2700 iterations using the default settings. You can therefore use the few lines of C that follow to check that the FLL has locked to the default frequency. I also configured the capacitors to suit the TI MSP430FG4618/F2013 Experimenter’s Board.

The program attempts to clear the oscillator fault flag OFIFG after the delay and checks that this was successful. If not, the delay loop is repeated. This is simple but the program will never leave the loop if OFIFG cannot be cleared. This could arise if ACLK fails or the

FLL has been incorrectly configured so that the desired frequency lies outside the range of the DCO. The DCO error flag DCOF is set if the DCO’s frequency tap is in either its bottom or its top position and this in turn sets OFIFG. DCOF clears when the tap is moved from its extremes. An FLL is much simpler than its analog equivalent, the phase-locked loop (PLL), and is far quicker to come into lock. Having said that, there appears to be no way of telling whether the FLL has locked—only if it fails so badly that it moves to its top or bottom tap, which sets DCOF.