The I2C clock SCL is provided by the master on the I2C bus. When the USCI is in master mode, BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slave mode, the bit clock generator is not used and the UCSSELx bits don't care.n The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multi-master mode, the maximum bit clock is fBRCLK/8.
The BITCLK frequency is given by:
fBitClock = fBRCLK/UCBRx
The minimum high and low periods of the generated SCL are:
slow,MIN = tHIGH,MIN = (UCBRx/2)/fBRCLK when UCBRx is even low,MIN = tHIGH,MIN = ((UCBRx – 1)/2)/fBRCLK when UCBRx is odd
The USCI clock source frequency and the Prescaler setting UCBRx must be chosen such that the minimum low and high period times of the I2C specification are met. During the arbitration procedure, the clocks from the different masters must be synchronized. A device that first generates a low period on SCL overrules the other devices, forcing them to start their low periods. SCL is then held low by the device with the longest low period. The other devices must wait for SCL to be released before starting their high periods. Figure 38-16 shows the clock synchronization. This allows a slow slave to slow down a fast master.
The USCI module supports clock stretching and also makes use of this feature as described in the Operation Mode sections. The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module already released SCL due to the following conditions:
- USCI is acting as master and a connected slave drives SCL low.
- USCI is acting as master and another master drives SCL low during arbiter traction.
The UCSCLLOW bit is also active if tin USCI holds SCL low because it is waiting as a transmitter for data being written into UCBxTXBUF or as a receiver for the data being read from UCBxRXBUF.
The UCSCLLOW bit might get set for a short time with each rising SCL edge because the logic observes the external SCL and compares it to the internally generated SCL.