The computer can be used to perform a specific task, only by specifying the necessary steps to complete the task. The collection of such ordered steps forms a ‘program’ of a computer. These ordered steps are the instructions. Computer instructions are stored in central memory locations and are executed sequentially one at a time. The control reads an instruction from a specific address in memory and executes it. It then continues by reading the next instruction in sequence and executes it until the completion of the program.

A computer usually has a variety of Instruction Code Formats. It is the function of the control unit within the CPU to interpret each instruction code and provide the necessary control functions needed to process the instruction. An n bit instruction that k bits in the address field and m bits in the operation code field come addressed 2k location directly and specify 2m different operation.

  • The bits of the instruction are divided into groups called fields.
  • The most common fields in instruction formats are:
  1. An Operation code field that specifies the operation to be performed.
  2. An Address field that designates a memory address or a processor register.
  3. A Mode field that specifies the way the operand or the effective address is determined.

n-1                     m-1                   k-1                                          0

                      Fig: Instruction format with mode field

The operation code field (Opcode) of an instruction is a group of bits that define various processor operations such as add, subtract, complement, shift etcetera. The bits that define the mode field of an instruction code specify a variety of alternatives for choosing the operands from the given address. Operation specified by an instruction is executed on some data stored in the processor register or in the memory location. Operands residing in memory are specified by their memory address. Operands residing in processor register are specified with a register address.

Types of Instruction

  • Computers may have instructions of several different lengths containing varying number of addresses.
  • The number of address fields in the instruction format of a computer depends on the internal organization of its registers.
  • Most computers fall into one of 3 types of CPU organizations:

Single accumulator organization:- All the operations are performed with an accumulator register. The instruction format in this type of computer uses one address field. For example: ADD X, where X is the address of the operands .

General register organization:- The instruction format in this type of computer needs three register address fields. For example: ADD R1,R2,R3

Stack organization:- The instruction in a stack computer consists of an operation code with no address field. This operation has the effect of popping the 2 top numbers from the stack, operating the numbers and pushing the sum into the stack. For example: ADD

Computers may have instructions of several different lengths containing varying number of addresses. Following are the types of instructions.

1. Three address Instruction

With this type of instruction, each instruction specifies two operand location and a result location. A temporary location T is used to store some intermediate result so as not to alter any of the operand location. The three address instruction format requires a very complex design to hold the three address references.

Format: Op X, Y, Z; X ß Y Op Z

Example: ADD X, Y, Z; X ß Y + Z

  • ADVANTAGE: It results in short programs when evaluating arithmetic
  • DISADVANTAGE: The instructions requires too many bits to specify 3

2. Two address instruction

Two-address instructions are the most common in commercial computers. Here again each address field can specify either a processor register, or a memory word. One address must do double duty as both operand and result. The two address instruction format reduces the space requirement. To avoid altering the value of an operand, a MOV instruction is used to move one of the values to a result or temporary location T, before performing the operation.

Format: Op X, Y;                                X ß X Op Y Example: SUB X, Y; X ß X - Y

3. One address Instruction

It was generally used in earlier machine with the implied address been a CPU register known as accumulator. The accumulator contains one of the operand and is used to store the result. One-address instruction uses an implied accumulator (Ac) register for all data manipulation. All operations are done between the AC register and a memory operand. We use LOAD and STORE instruction for transfer to and from memory and Ac register. Format: Op X; Ac ß Ac Op X

Example: MUL X;  Ac ß Ac * X

4. Zero address Instruction

It does not use address field for the instruction like ADD, SUB, MUL, DIV etc. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The name “Zero” address is given because of the absence of an address field in the computational instruction.

Format: Op; TOS ß TOS Op (TOS – 1) Example: DIV; TOS ß TOS DIV (TOS – 1)

Example: To illustrate the influence of the number of address on computer programs, we will evaluate the arithmetic statement X=(A+B)*(C+D) using Zero, one, two, or three address instructions.

  1. Three-Address Instructions:

ADD R1, A, B;           R1 ß M[A] + M[B]

ADD R2, C, D;                                 R2 ß M[C] + M[D] MUL X, R1,R2;                            M[X] ß R1 * R2

It is assumed that the computer has two processor registers R1 and R2. The symbol M[A] denotes the operand at memory address symbolized by A.

  1. Two-Address Instructions:   MOV R1, A;  R1 ß M[A] ADD R1, B;              R1 ß R1 + M[B]

MOV R2, C;    R2 ß M[C] ADD R2, D;    R2 ß R2 + M[D] MUL R1, R2; R1 ß R1 * R2 MOV X, R1; M[X] ß R1

  1. One-Address Instruction: LOAD A; Ac ß M[A]

ADD B;           Ac ß Ac + M[B] STORE T;          M[T] ß Ac LOAD C;                    Ac ß M[C] ADD D;         Ac ß Ac + M[D] MUL T;      Ac ß Ac * M[T] STORE X;      M[X] ß Ac

Here, T is the temporary memory location required for storing the intermediate result.

  1. Zero-Address Instructions: PUSH A; TOS ß A

PUSH B;         TOS ß B

ADD;              TOS ß (A + B)

PUSH C;         TOS ß C

PUSH D;         TOS ß D

ADD;              TOS ß (C + D)

MUL;              TOS ß (C + D) * (A + B)

POP X ;           M[X] ß TOS