The VLO is an internal RC oscillator that runs at around 12 kHz and can be used instead of LFXT1 in some newer devices. It saves the cost and space required for a crystal and reduces the current drawn. The data sheet for the F2013 shows that LFXT1 draws about 0.8_A, which falls to 0.5_A with the VLO. (Both are impressively small currents.) Of course, this comes at a cost: accuracy and stability. The same data sheet quotes a range of frequency for five from 4 to 20 kHz. This looks terrible at first sight but a closer reading shows that it covers the full operating range of the device in voltage and temperature.
A variation of 10◦C changes the frequency by about 5% instead of 5 ppm for a crystal.
You would not use the VLO for serious timing. On the other hand, its purpose is often to wake the device periodically to check whether any inputs have changed, and accuracy is not important. ACLK is taken from LFXT1 by default even where the VLO is present. This means that current is wasted in LFXT1 and that pins P2.6 and P2.7 in the F20xx are configured for a crystal. It is usually a good idea to reconfigure the BCM+ to use the VLO and redirect the port Digitally Controlled Oscillator, DCO:
One of the aims of the original design of the MSP430 was that it should be able to start rapidly at full speed from a low-power mode, without waiting a long time for the clock to settle. Early versions of the DCO started in 6_s, which has been reduced to 1–2_s in the MSP430F2xx family. There are no erratic pulses: The output from the DCO starts cleanly after this delay. The stability and accuracy also improved significantly since the early days of the MSP430 and calibration values are now stored for a set of frequencies, giving an accuracy of 1–2%.
The frequency can be controlled through sets of bits in the module’s registers at three levels. The numbers are taken from the datasheet for the F2013. The first two levels set the DCO to a constant frequency:
RSELx: Selects one of 16 coarse ranges of frequency. The frequencies in each range are larger than those in the one below by a factor of 1.3–1.4. The overall range is about 0.09–20 MHz. DCOM: Selects one of eight steps within each range. Each step increases the frequency by about 8%, giving a factor of 1.7 from the bottom to the top of the range. Thus the ranges overlap slightly. Figure 5.9 shows the frequency of the DCO in the low part of its range as a function of RSELx and DCOx. There is roughly a constant ratio between values so a logarithmic scale would be needed to show the full range clearly. TI does not provide much information about the innards of the DCO. It appears to be based on a type of RC oscillator whose frequency is programmed by a current, which is selected by RSEL. This feeds a ring counter whose period is adjusted with DCO. An external resistor Rosc can be connected to some devices to regulate the current instead of RSEL.
This could improve the stability of the frequency in older devices but is less useful in newer ones. It could also be used to control the frequency by an external analog signal.
Finer control of the average frequency is obtained by modulating the frequency of the oscillator between the selected value of DCO and the next step up (DCO+1). This needs DCO < 7 of course. Each period of 32 clock cycles contains MOD cycles with the higher frequency given by (DCO+1) and (32−MOD) cycles with the lower frequency given by DCO. The average period over these 32 cycles is therefore
The DCO does not simply produce MOD pulses of one frequency followed by (32−MOD) of the other but mixes them thoroughly. For example, setting MOD = 16 gives an equal number of pulses of the two frequencies and they alternate: Each period given by DCO is followed by one given by (DCO+1). This is shown on the oscilloscope in Figure 5.10. The top trace shows the clean square wave seen in a single sweep. There is a longer period (DCO = 0) in the center with shorter periods (DCO = 1) on either side.
The lower trace shows repeated sweeps with persistence, as would be seen on an analog oscilloscope. The clock now appears to have jitter on the falling edges because of the two different periods, but the positive edges, which are used for triggering, all overlap. A truly periodic clock is found over the full period of 32 pulses (or fewer in special cases, such as that shown here). The values of RSEL, DCO, and MOD can be changed at any time to alter the frequency. Modulation can be turned off by setting MOD = 0 if a constant period is more important than an accurate, average frequency. The modulator serves little purpose if the DCO runs freely without calibration. There is nearly a factor of 2 between the minimum and maximum frequencies given in the data sheet for given values of RSEL and DCO, although this covers the full range of temperature and supply voltage. Therefore it is pointless to specify the frequency better than can be done with RSEL and DCO alone. A possible advantage of modulation is that there is less electromagnetic interference (EMI) from the clock because the energy is spread over a wider range of frequencies, but this is not a large effect with periods that are only 8% apart. A method to reduce EMI further is described in the application note Spread-Spectrum
Clock Source Using an MSP430 (slaa291). Modulation is also used to generate accurate baud rates for asynchronous communication as we shall see in the
The write to BCSCTL1 affects the whole byte, not just the RSELx bits, and clears the other bits. It may therefore be necessary to reconfigure the other functions controlled by this register (XT2OFF, XTS, and DIVAx) but the defaults are usually satisfactory. The calibration is typically accurate within about 2% over the full range of operating conditions and to 0.2% at room temperature with a 3V supply. This is still not as good as a crystal but is impressive compared with a “plain vanilla” RC oscillator, whose frequency might vary by ±25%.
The F20xx has calibrated frequencies of 1, 8, 12, and 16 MHz. The values are stored in segment A of the information memory, which is locked by default against programming and erasing. You should not be able to overwrite these values by accident when downloading your program unless you override the settings in the debugger
Control of the Clock Module through the Status Register
The clock module is controlled by 4 bits in the status register as well as its own peripheral registers. This is because of the intimate connection between clocks and low-power modes, which is discussed fully in the section “Low-Power Modes of Operation” on page 198. It is rarely necessary to alter these bits directly because there are intrinsic functions or predefined constants for each low-power mode. All bits are clear in the full-power, active mode. This is the main effect of setting each bit in the MSP430F2xx:
CPUOFF disables MCLK, which stops the CPU and any peripherals that use MCLK.
SCG1 disables SMCLK and peripherals that use it.
SCG0 disables the DC generator for the DCO (disables the FLL in the MSP430x4xx family).
OSCOFF disables VLO and LFXT1.
It is not as straightforward as this because the effects of the different bits interact with other. For example, setting only SCG0 and SCG1 does not stop the DCO if it supplies MCLK, because that would paralyze the processor. The DCO stops only if the source of MCLK is also switched to LFXT1 or VLO. This is illustrated by the code example msp430x20x3_1_vlo. Here are the relevant two lines. You might worry that the first line would stop the CPU but it does not; the DCO remains active while MCLK