• In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1.
  • In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system.
  • The remaining components in the system are latches, transceiverseivers, clock generators, memory, and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system.
  • Latches are generally buffered output D-type flip-flops like 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.
  • Transreces are bidirectional buffers and sometimes they are called data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals.
  • They are controlled by two signals namely, DEN and DT/R.

 

The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and user program storage.

  • Usually, EPROMs are used for monitor storage, while RAM is for users' program storage. A system may contain I/O devices.
  • The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized into two parts, the first is the timing diagram for the reading cycle and the second is the timing diagram for the write cycle.
  • The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.
  • The BHE and A0 signals address low, high, or both bytes. From T1 to T4, the M/IO signal indicates a memory or I/O operation.
  • At T2, the address is removed from the local bus and is sent to the output. The bus is then treated. The read (RD) control signal is also activated in T2.
  • The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.
  • The addressed device will drive the READY line high. When the processor returns the read signal to a high level, the addressed device will again tristate its bus drivers.
  • A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.
  • The data remains on the bus until the middle of the T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
  • The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or written.

Maximum Mode 8086 System

  • In the maximum mode, the 8086 is operated by strapping the MN/MX pin to the ground.
  • In this mode, the processor derives the status signals S2, S1, and S0. Another chip called the bus controller derives the control signal using this status information.
  • In the maximum mode, there may be more than one microprocessor in the system configuration.
  • The components in the system are the same as in the minimum mode system.
  • The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR (for memory and I/O devices), DEN, DT/R, ALE, etc. using the information by the processor on the status lines.
  • The bus controller chip has input lines S2, S1, S0, and CLK. These inputs to 8288 are driven by the CPU.
  • It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC, and AIOWC. The AEN, IOB, and CEN pins are especially useful for multiprocessor systems
  • AEN and IOB are generally grounded.  The CEN pin is usually tied to +5V.  The significance of the MCE/PDEN output depends upon the status of the IOB pin.
  • If IOB is grounded, it acts as a master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations.
  • INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or an interrupting device.
  • IORC and IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. •The MRDC and MWTC are memory read command and memory write command signals respectively, and may be used as memory read or write signals.
  • All these command signals instructs the memory to accept or send data from or to the bus. •For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.
  • Here the only difference in the timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals. •R0, S1, and S2 are set at the beginning of the bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.
  • In T2, 8288 will set DEN=1 thus enabling transceivers, and for input, it will activate MRDC or IROC. These signals are activated until T4. For output, the AMWC or AIOWC is activated from T2 to T4, and MWTC or IOWC is activated from T3 to T4. •The status bit S0 to S2 remains active until T3 and becomes passive during T3 and T4.
  • If reader input is not activated before T3, a wait state will be inserted between T3 and T4.