L1 and L2 Cache

On-chip cache (L1 Cache)

  • It is the cache memory on the same chip as the processor, the on-chip cache. It reduces the processor's external bus activity and therefore speeds up execution times and increases overall system performance.
  • Requires no bus operation for cache hits
  • Short data paths and same speed as other CPU transactions

Off-chip cache (L2 Cache)

  • It is the external cache which is beyond the processor. If there is no L2 cache and processor makes an access request for memory location not in the L1 cache, then processor must access DRAM or ROM memory across the Due to this typically slow bus speed and slow memory access time, this results in poor performance. On the other hand, if an L2 SRAM cache is used, then frequently the missing information can be quickly retrieved.
  • It can be much larger
  • It can be used with a local bus to buffer the CPU cache-misses from the system bus

Unified and Split Cache

  • Unified Cache
    • Single cache contains both instructions and data. Cache is flexible and can balance “allocation” of space to instructions or data to best fit the execution of the program.
    • Has a higher hit rate than split cache, because it automatically balances load between data and instructions (if an execution pattern involves more instruction fetches than data fetches, the cache will fill up with more instructions than data)
    • Only one cache need be designed and implemented

Split Cache

  • Cache splits into two parts first for instruction and second for data. Can outperform unified cache in systems that support parallel execution and pipelining (reduces cache contention)
  • Trend is toward split cache because of superscalar CPU’s
  • Better for pipelining, pre-fetching, and other parallel instruction execution designs
  • Eliminates cache contention between instruction processor and the execution unit (which uses data)