• PCI is a popular high bandwidth, processor independent bus that can function as mezzanine or peripheral bus.
  • PCI delivers better system performance for high speed I/O subsystems (graphic display adapters, network interface controllers, disk controllers etc.)
  • PCI is designed to support a variety of microprocessor based configurations including both single and multiple processor system.
  • It makes use of synchronous timing and centralised arbitration scheme.
  • PCI may be configured as a 32 or 64-bit bus.
  • Current Standard
    • up to 64 data lines at 33Mhz
    • requires few chips to implement
    • supports other buses attached to PCI bus
    • public domain, initially developed by Intel to support Pentium-based systems
    • supports a variety of microprocessor-based configurations, including multiple processors
    • uses synchronous timing and centralized arbitration

Typical Desktop System

Note: Bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s I/O capability.

Typical Server System

Note: In a multiprocessor system, one or more PCI configurations may be connected by bridges to the processor’s system bus.

PCI Bus Lines

  • Systems lines
    • Including clock and reset
  • Address & Data
    • 32 time mux lines for address/data
    • Interrupt & validate lines
  • Interface Control
  • Arbitration
    • Not shared
    • Direct connection to PCI bus arbiter
  • Error lines
  • Interrupt lines
    • Not shared
  • Cache support
  • 64-bit Bus Extension
    • Additional 32 lines
    • Time multiplexed
    • 2 lines to enable devices to agree to use 64-bit transfer
  • JTAG/Boundary Scan
    • For testing procedures

PCI Commands

  • Transaction between initiator (master) and target
  • Master claims bus
  • Determine type of transaction
    • eg. I/O read/write
  • Address phase
  • One or more data phases

PCI Enhancements: AGP

  • AGP – Advanced Graphics Port
    • Called a port, not a bus because it only connects 2 devices