Receive timing error consists of two error sources. The first is the bit-to-bit timing error similar to the transmit bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USCI module. Figure 36-11 shows the asynchronous timing errors between data on the UCAxRXD pin and the internal baud-rate clock. This results in an additional synchronization error. The synchronization error tSYNC is between –0.5 BRCLKs and +0.5 RCLKs, independent of the selected baud rate generation mode.
Menu
-
Information Technology
Artificial Intelligence C Programming Cloud Computing Computer Graphics Computer Network Computer Organization and Architecture Data Communications Data Mining and Data Warehousing Data Structure and Algorithm Database Management System
-
Management
Adventure in English II Banking Business Environment Business Law Business Statistics Corporate Finance Financial Institutions and Market Financial Management Fundamentals of Sociology General Psychology
- Subjects
- Universities