The sampling of the ADC input takes 12 ADCLK cycles; this means the sampling gate is open during this time (12 s at1 MHz). The sampling time is identical for the range decision sample and the data conversion sample. The input circuitry of an ADC input pin, Ax, can be seen simplified as an RC low pass filter during the sampling period (12/ADCLK): 2 k in series with 42 pF. The 42-pF capacitor (the sample-and-hold capacitor) must be charged during the 12 ADCLK cycles to (nearly) the final voltage value to be measured, or to within 2–14 of this value.
The sample time limits the internal resistance, Ri, of the source to be measured: ((Ri _2 ),42 pF _12
ln_214_ADCLK
Solved for Ri with ADCLK = 1 MHz this results in:
Ri _ 27.4 k
This means, that for the full resolution of the ADC, the internal resistance of the input signal must be lower than 27.4 k. If a resolution of n bits is sufficient, then the internal resistance of the ADC input source can be higher: