UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit clock generator is not used, and the UCSSELx bits don't care. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer.
The 16-bit value of UCBRx in the bit rate control registers (UCxxBR1 and UCxxBR0) is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be generated in master mode is BRCLK. Modulation is not used in SPI mode, and UCAxMCTL should be cleared when using SPI mode for USCI_A.
The UCAxCLK/UCBxCLK frequency is given by:
bit clock = fBRCLK / UCBRx
If UCBRx = 0, fBitClock = fBRCLK
Even UCBRx settings result in even divisions and, thus, generate a bit clock with a 50/50 duty cycle.
Odd UCBRx settings result in odd divisions. In this case, the high phase of the bit clock is one BRCLK cycle longer than the low phase. When UCBRx = 0, no division is applied to BRCLK, and the bit clock equals BRCLK.
Serial Clock Polarity and Phase
The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI. The timing for each case is shown in Figure
Using the SPI Mode With Low-Power Modes
The USCI module provides automatic clock activation for use with low-power modes. When the USCI clock source is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition.
After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. In SPI slave mode, no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled. The receive or transmit interrupt can wake up the CPU from any low-power mode.
