The USB buffer memory contains the data buffers for all endpoints and SETUP packets. In that the buffers for endpoints 1 to 7 are flexible, there are USB buffer configuration registers that define them, and these too are in the USB buffer memory. (Endpoint 0 is defined with a set of registers in the USB control register space.) Storing these in open memory allows for efficient, flexible use, which is advantageous because the use of these endpoints is very application-specific.

This memory is implemented as "multiport" memory, in that it can be accessed both by the USB buffer manager and also by the CPU and DMA. The SIE allows CPU or DMA access but reserves priority. As a result, CPU or DMA access is delayed using wait states if a conflict arises with an SIE access. When the USB module is disabled (USBEN = 0), the buffer memory behaves like regular RAM. When changing the state of the USBEN bit (enabling or disabling the USB module), the USB buffer memory should not be accessed within four clocks before and eight clocks after changing this bit, as doing so reconfigure the access method to the USB memory.

Accessing the USB buffer memory by CPU or DMA is only possible if the USB PLL is active. When a host requests suspend conditions the application software (for example, USB stack) of the client has to switch off the PLL within 10 ms. Note that the MSP430 USB suspend interrupt occurs around 5 ms after the host request.

Each endpoint is defined by a block of six configurations "registers" (based on RAM, they are not true registers in the strict sense of the word). These registers specify the endpoint type, buffer address, buffer size, and data packet byte count. They define an endpoint buffer space that is 1904 bytes in size. An additional 24 bytes are allotted to three remaining blocks – the EP0_IN buffer, the EP0_OUT buffer, and the SETUP packet buffer (see Table 42-3).

The software can configure each buffer according to the total number of endpoints needed. Single or double buffering of each endpoint is possible. Unlike the descriptor registers for endpoints 1 to 7, which are defined as memory entries in USB RAM, endpoint 0 is described by a set of four registers (two for output and two for input) in the USB control register set. Endpoint 0 has no base-address register since these addresses are hardwired. The bit positions have been preserved to provide consistency with endpoint_n (n = 1 to 7).