• When a line is to be replaced, must update the original copy of the line in main memory if any addressable unit in the line has been changed
  • If a block has been altered in cache, it is necessary to write it back out to main memory before replacing it with another block (writes are about 15% of memory references)
  • Must not overwrite a cache block unless main memory is up to date
  • I/O modules may be able to read/write directly to memory
  • Multiple CPU’s may be attached to the same bus, each with their own cache

Write Through

  • All write operations are made to main memory as well as to cache, so main memory is always valid
  • Other CPU’s monitor traffic to main memory to update their caches when needed
  • This generates substantial memory traffic and may create a bottleneck
  • Anytime a word in cache is changed, it is also changed in main memory
  • Both copies always agree
  • Generates lots of memory writes to main memory
  • Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date
  • Lots of traffic
  • Slows down writes
  • Remember bogus write through caches!

Write back

  • When an update occurs, an UPDATE bit associated with that slot is set, so when the block is replaced it is written back first
  • During a write, only change the contents of the cache
  • Update main memory only when the cache line is to be replaced
  • Causes “cache coherency” problems -- different values for the contents of an address are in the cache and the main memory
  • Complex circuitry to avoid this problem
  • Accesses by I/O modules must occur through the cache
  • Multiple caches still can become invalidated, unless some cache coherency system is used. Such systems include:
    • Bus Watching with Write Through - other caches monitor memory writes by other caches (using write through) and invalidates their own cache line if a match
    • Hardware Transparency - additional hardware links multiple caches so that writes to one cache are made to the others
    • Non-cacheable Memory - only a portion of main memory is shared by more than one processor, and it is non-cacheable