In synchronous mode, the USCI connects the device to an external system via three or four pins:
UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit is set, and
SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits. SPI mode features include:
- 7-bit or 8-bit data length
- LSB-first or MSB-first data transmit and receive
- 3-pin and 4-pin SPI operation
- Master or slave modes
- Independent transmit and receive shift registers
- Separate transmit and receive buffer registers
- Continuous transmit and receive operation
- Selectable clock polarity and phase control
- Programmable clock frequency in master mode
- Independent interreceivingpability for receive and transmit
- Slave operation in LPM4
USCI Operation – SPI Mode
In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master.
Three or four signals are used for SPI data exchange:
- UCxSIMO – slave in, master out
Master mode: UCxSIMO is the data output line. Slave mode: UCxSIMO is the data input line.
- UCxSOMI – slave out, master in
Master mode: UCxSOMI is the data input line. Slave mode: UCxSOMI is the data output line.
- UCxCLK – USCI SPI clock Master mode: UCxCLK is an output.
Slave mode: UCxCLK is an input.
- UCxSTE – slave transmit enable
Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode.